3d chip assemblies using stacked leadframes

ABSTRACT

A stacked-chip assembly including a plurality of IC chips or die that are stacked, and a plurality of stacked leads. Leads from separate leadframes may be bonded together so as to tie corresponding metal features of the various chips to a same ground, signal, or power rail. Each leadframe may include a center paddle, which is disposed between two chips in the stack. The center paddle may function as one or more of a thermal conduit and common electrical rail (e.g., ground). The leadframes may be employed without the use of any bond wires with leads bonded directly to bond pads of the chips. A first IC chip may be mounted to a base leadframe and subsequent die-attach leadframes and IC chips are stacked upon the first IC chip and base leadframe. The die-attach leadframes may be iteratively bonded to an underlying leadframe and the bonded stacked leads stamped out of their respective leadframe sheets.

CLAIM FOR PRIORITY

This application is a continuation of prior U.S. patent application Ser.No. 15/338,162, filed on Oct. 28, 2016 and titled “3D CHIP ASSEMBLIESUSING STACKED LEADFRAMES”, which is incorporated by reference in itsentirety.

BACKGROUND

There are many integrated circuit (IC) chip, or die, packagingtechnologies. A number of advanced IC packages include a plurality of ICchips in a stack, which reduce the footprint of the IC chips to improvedevice density within a given platform (e.g., mobile device, computer,automobile). FIG. 1A illustrates a plan view of a conventionalstacked-chip assembly 101. FIG. 1B illustrates a cross-sectional view ofstacked-chip assembly 101. As shown, IC chip 111 is stacked over IC chip110, IC chip 112 is further stacked over IC chip 111, and IC chip 113 isfurther stacked over IC chip 112. Between each IC chip is a die attachmaterial 140 (e.g., paste or film). To accommodate electrical connection(e.g., power, signal, ground) by wire bonds, stacked chips may belaterally offset or displaced in one or more dimensions relative to anunderlying/overlying chip. For example, chip 111 is laterally offset inthe x-dimension from an edge of chip 110. Similarly, chip 112 islaterally offset in the x-dimension from an edge of chip 111. Such an ICchip stack requires a footprint that is a function of both the chip sizeand the cumulative chip offset required for the wire bonds. For example,in FIG. 1B, the stack footprint is a function of both the chip lengthL_(c) and offset length L_(o). As such, staggering the chips increasespackage size.

As further shown in FIGS. 1A and 1B, wire bonds may be waterfalled froma top most chip (e.g., 113) to successively lower chips until landing ona package substrate 105. Such waterfalled wire bonds are typical inapplications where the chips in the stack are the same and various padson each chip may be powered, grounded, or signaled concurrently withcorresponding pads on another chip. Such an architecture is common for aNAND flash memory chip, which often accommodate metal features on one ortwo sides of the chip (e.g., opposite edges laterally separated in thex-dimension in FIG. 1A, 1B). In addition to the offset increasingpackage footprint, package substrate 105 increases the z-thickness ofassembly 101, and all increases the cost of the package assembly.

Heat generated by the stacked chips during operation of assembly 101 isanother issue. For example, heat generated by chip 110 may need toconduct through chip 111, 112, and 113 to reach a heat sink disposedover the chip stack (e.g., landed on chip 113). The bulk materialcomposition (e.g., silicon) often has a relatively low thermalconductivity, making it difficult to adequately cool chips within astacked-chip assembly.

BRIEF DESCRIPTION OF THE DRAWINGS

The material described herein is illustrated by way of example and notby way of limitation in the accompanying figures. For simplicity andclarity of illustration, elements illustrated in the figures are notnecessarily drawn to scale. For example, the dimensions of some elementsmay be exaggerated relative to other elements for clarity. Further,where considered appropriate, reference labels have been repeated amongthe figures to indicate corresponding or analogous elements. In thefigures:

FIG. 1A illustrates a top-down plan view of a conventional stacked-chipassembly;

FIG. 1B illustrates a cross-sectional view of a conventionalstacked-chip assembly;

FIG. 2A illustrates a top-down plan view of a stacked-chip assemblyincluding stacked leads, in accordance with an embodiment;

FIG. 2B illustrates a cross-sectional view of a stacked-chip assemblyincluding stacked leads, in accordance with an embodiment;

FIGS. 3, 4, 5, and 6 illustrate cross-sectional views of stacked chipassemblies with stack leads, in accordance with alternate embodiments;

FIG. 7A illustrates a top-down plan view of a stacked-chip assemblyincluding a stacked leads, in accordance with an alternate embodiment;

FIG. 7B illustrates a cross-sectional view of a stacked-chip assemblyincluding stacked leads, in accordance with an alternate embodiment;

FIG. 8A illustrates a plan view of a base leadframe, in accordance withsome embodiments;

FIG. 8B illustrates a plan view of a die-attach leadframe, in accordancewith some embodiments;

FIG. 8C illustrate leadframe sheets, which may be employed inreel-to-reel packaging technology, in accordance with some embodiments;

FIG. 9A illustrates a flow diagram of a method for assembling a chipassembly including stacked leads, in accordance with some embodiments;

FIG. 9B illustrates cross-sectional views of a stacked-chip assembly asselected operations in the assembly method shown in FIG. 9A isperformed, in accordance with some embodiments;

FIG. 9C illustrates a flow diagram of an alternate method for assemblinga chip assembly including stacked leads, in accordance with someembodiments;

FIG. 10 is a functional block diagram of an electronic computing device,in accordance with some embodiments; and

FIG. 11 illustrates a mobile computing platform and a data servermachine employing a memory chip stack include stacked leads, inaccordance with some embodiments.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments are described with reference to the enclosed figures. Whilespecific configurations and arrangements are depicted and discussed indetail, it should be understood that this is done for illustrativepurposes only. Persons skilled in the relevant art will recognize thatother configurations and arrangements are possible without departingfrom the spirit and scope of the description. It will be apparent tothose skilled in the relevant art that techniques and/or arrangementsdescribed herein may be employed in a variety of other systems andapplications other than what is described in detail herein.

Reference is made in the following detailed description to theaccompanying drawings, which form a part hereof and illustrate exemplaryembodiments. Further, it is to be understood that other embodiments maybe utilized and structural and/or logical changes may be made withoutdeparting from the scope of claimed subject matter. It should also benoted that directions and references, for example, up, down, top,bottom, and so on, may be used merely to facilitate the description offeatures in the drawings and are not intended to restrict theapplication of claimed subject matter. Therefore, the following detaileddescription is not to be taken in a limiting sense and the scope ofclaimed subject matter is defined solely by the appended claims andtheir equivalents.

In the following description, numerous details are set forth, however,it will be apparent to one skilled in the art, that embodiments may bepracticed without these specific details. In some instances, well-knownmethods and devices are shown in block diagram form, rather than indetail, to avoid obscuring inventive aspects of the exemplaryembodiments. References throughout this specification to “an embodiment”or “one embodiment” mean that a particular feature, structure, function,or characteristic described in connection with the embodiment isincluded in at least one embodiment. Thus, the appearances of the phrase“in an embodiment” or “in one embodiment” in various places throughoutthis specification are not necessarily referring to the same embodiment.Furthermore, the particular features, structures, functions, orcharacteristics may be combined in any suitable manner in one or moreembodiments. For example, a first embodiment may be combined with asecond embodiment anywhere the particular features, structures,functions, or characteristics associated with the first and secondembodiments are not mutually exclusive.

As used in the description of the exemplary embodiments and the appendedclaims, the singular forms “a”, “an” and “the” are intended to includethe plural forms as well, unless the context clearly indicatesotherwise. It will also be understood that the term “and/or” as usedherein refers to and encompasses any and all possible combinations ofone or more of the associated listed items. As used throughout thisdescription, and in the claims, a list of items joined by the term “atleast one of” or “one or more of” can mean any combination of the listedterms. For example, the phrase “at least one of A, B or C” can mean A;B; C; A and B; A and C; B and C; or A, B and C.

The terms “coupled” and “connected,” along with their derivatives, maybe used herein to describe functional or structural relationshipsbetween components. It should be understood that these terms are notintended as synonyms for each other. Rather, in particular embodiments,“connected” may be used to indicate that two or more elements are indirect physical, optical, or electrical contact with each other.“Coupled” may be used to indicated that two or more elements are ineither direct or indirect (with other intervening elements between them)physical, optical, or electrical contact with each other, and/or thatthe two or more elements co-operate or interact with each other (e.g.,as in a cause an effect relationship).

The terms “over,” “under,” “between,” and “on” as used herein refer to arelative position of one component or material layer with respect toother components or layers where such physical relationships arenoteworthy. For example in the context of material layers, one layerdisposed over or under another layer may be directly in contact with theother layer or may have one or more intervening layers. Moreover, onelayer disposed between two layers may be directly in contact with thetwo layers or may have one or more intervening layers. In contrast, afirst layer “on” a second layer is in direct contact with that secondlayer. Similar distinctions are to be made in the context of componentassemblies.

As described in greater detail below, a stacked-chip assembly includes aplurality of IC chips or die that are stacked, and a plurality ofstacked leads. In some embodiments, leads from separate leadframes arebonded together at a periphery of the stack so as to tie correspondingmetal features of the various chips to a same ground, signal, or powerrail. In some embodiments, each leadframe includes a center paddle,which is disposed between two chips in the stack. The center paddle mayfunction as a common rail (e.g., ground) and/or thermal conduit. In someembodiments, the leadframes are employed without the use of any bondwires, and leads of the leadframes may be bonded directly to the metalfeatures (e.g., bond pads) of the chips. In some embodiments, a first ICchip is mounted to a base leadframe and subsequent die-attach leadframesand IC chips are stacked upon the first IC chip and base leadframe. Thedie-attach leadframes may be iteratively bonded to an underlyingleadframe and the bonded stacked leads stamped out of their respectiveleadframe sheets. In some embodiments, individual IC chips may beiteratively mounted to individual leadframes. Individualleadframe-mounted IC chips may then be stacked, and the stack stamped tobond and/or cut the stacked leads from their respective leadframesheets.

FIG. 2A illustrates a top-down plan view of a stacked IC chip assembly201, in accordance with some embodiments. Assembly 201 includes a paddle245D, that may be of any material having suitable electrical and/or orthermal conductivity, such as any elemental metal or metal alloy (i.e.,metallic). Paddle 245D is disposed over a top-most IC chip 113. At leastone electrically conductive lead of lead stacks 235A-235N is coupled toan electrically conductive feature of IC chip 113, such as a bond pad,pin, or post. Each lead stack 235A-235N includes a first portion 250 anda second portion 270. Within lead portion 250, leads of each lead stack235A-235N are electrically connected (e.g., thermo-compression bonded).Within lead portion 270, each lead of lead stack 235A-235N iselectrically coupled to at least one IC chip of a chip stack. In theexemplary embodiments illustrated in FIG. 2A, lead portion 250 is at aperiphery of the IC stack demarked by the edge of IC chip 113. Spatiallyco-located leads coupling to different IC chips in the stack areelectrically tied together at a peripheral location beyond the IC chipedge. As shown, each lead stack 235A-235N is physically separated andelectrically isolated from it's nearest neighbors, enabling each stackto maintain different ground/signal/power levels at each I/O of IC chip113. Each lead stack 235A-235N may also be physically and electricallyindependent of paddle 245D, as shown.

FIG. 2B illustrates a cross-sectional view of a stacked-chip assembly201, in accordance with an embodiment. The chip stack includes IC chips110, 111, 112, 113, which may each be any IC chip. In some embodiments,all of IC chips 110-113 have substantially the same footprint (e.g.,same chip length L_(c)) and substantially the same pin-out layout (e.g.,bond pad locations). In some advantageous embodiments, IC chips 110-113are flash memory chips, such as NAND chips. Depending on the IC chip,chip z-thickness may vary. Embodiments herein are not limited toultra-thin chips, and IC chips with a thickness of 100 μm, or more arecompatible. Likewise, embodiments herein are also compatible withultra-thin chips having a thickness of 100 μm, or less. As furthershown, lead stack 235N includes a base lead 220 and one or moredie-attach leads 230. In the exemplary embodiment with four chips110-113, there are four stacked die-attach leads 230A, 230B, 230C, and230D. In the embodiments exemplified by FIG. 2B, lead portion 270 ofeach die-attach lead 230A-230D makes direct contact with a bond pad (notdepicted) disposed on a face (e.g., front-side surface) of one IC chip110-113. As such, along the z-axis, die-attach leads 230A-230D areinterdigitated with IC chips 110-113. Each die-attach lead 230A-230Dfurther includes lead portion 250, which contacts one or more other lead(e.g., another die-attach lead 230 and/or base lead 220). In someexemplary embodiments, die-attach lead 230A is directly (e.g.,thermo-compression) bonded to base lead 220, die-attach lead 230A isthermo-compression bonded to die-attach lead 230B, die-attach lead 230Cis thermo-compression bonded to die-attach lead 230B, and die-attachlead 230D is thermo-compression bonded to die-attach lead 230C. Althoughthe cross-sectional view shown in FIG. 2B illustrates only two side ofthe chip stack, a similar arrangement may be present on the orthogonalsides. Alternatively, independent signal leads (e.g., chip enable, etc.)that are specific to each chip the stack are not stacked in the mannerillustrated in FIG. 2B (i.e., not co-located and bonded together).

In some embodiments, a paddle is disposed between two stacked IC chips.The intervening paddle may have high thermal and/or electricalconductivity and may enhance removal of heat laterally from astacked-chip assembly relative to stacks lacking such a paddle. In someembodiments, there is a metallic paddle disposed between every IC chipwithin a stack. Each paddle may be physically and electricallyindependent of one or more of the lead stacks. In some embodiments,every paddle is physically and electrically independent of all of thelead stacks. There may also be a base paddle upon which all the IC chipsare stacked and a topmost die-attach paddle disposed over the entirechip stack. In FIG. 2B for example, IC chip 110 is disposed over a basepaddle 240. Base paddle 240 may be of the same material composition andthickness as base lead 220; the two features having been stamped out ofthe same leadframe sheet, for example. Exemplary leadframe materialsinclude Cu (in elemental or an alloyed for) and stainless steel (e.g.,alloy 42). However, other metals (elemental or alloyed) may also beemployed. Depending on the leadframe material, the leadframe may havesurface finish, such as, but not limited to, an adhesion layer (e.g.,Ni) and a bonding layer (e.g., Au). Exemplary leadframe thicknessesrange from 90-200 μm, but thinner embodiments (e.g., 24 μm, or less) arealso possible.

Intervening between IC chip 111 and 110 is a die-attach paddle 245A.Die-attach paddle 245A may be of the same material composition andthickness as die-attach lead 230A, the two features having been stampedout of the same sheet, for example. Similar die-attach paddles aredisposed between chips 112 and 111, as well as between chips 113 and112. In some embodiments, a base paddle 240 and base lead 220 arethicker and/or have a different composition than die-attach paddle 245Aand die-attach lead 230A, for example to provide a more substantialassembly substrate. For example, base paddle 240 and base lead 220 maybe at least 50 μm in thickness (e.g., z-axis), whereas die-attach paddle245A and die-attach lead 230A may be less than 25 μm in thickness.Exemplary die-attach leadframe materials include Cu (in elemental or analloyed for) and stainless steel (e.g., alloy 42). However, other metals(elemental or alloyed) may also be employed. Depending on the leadframematerial, the leadframe may have surface finish, such as, but notlimited to, an adhesion layer (e.g., Ni) and a bonding layer (e.g., Au).In some further embodiments, a base paddle (e.g., 240) has a largerfootprint than a die-attach paddle (e.g., 245A). Such architecturalfeatures are indicative of the base leadframe functioning as a stackedlead assembly substrate. In addition to serving as the assemblysubstrate, base paddle 240 may also provide an electrical connection(e.g., ground or power) to the IC chip, if desired. In alternativeembodiments, for example where an IC chip is flipped over relative aleadframe, the base paddle area may be substantially equal to that of adie-attach leadframe with every leadframe in the stack then making thesame number of electrical connections to the chip, as described furtherbelow.

In some embodiments, a paddle disposed between two stacked IC chipsmakes thermal contact with a heat sink (not depicted). The heat sink maybe disposed over, or adjacent to, IC chip stack assembly 201. The paddle(e.g., paddle ends 246 shown in FIG. 2A) may by thermally coupled to aheat sink on a substrate (not depicted). Alternatively, paddle ends 246may be thermally coupled to a heat sink disposed on or above paddle245D. In some embodiments where a paddle is disposed over every IC chipin the stack, a portion of the paddle at the periphery of the chip stackmay be further connected (e.g., directly bonded together) to thermallytie each chip to a common heat sink.

In some embodiments, a paddle disposed between two stacked IC chipsmakes electrical contact to a metal feature on one or more IC chip. Themetal feature, such as, but not limited to, a bond pad may makeelectrical contact with the paddle. The paddle (e.g., paddle ends 246shown in FIG. 2A) may further contact a metal feature on a substrate(not depicted) that provides a reference potential, such as, but notlimited to, a ground plane. In some embodiments where a paddle isdisposed over every IC chip in the stack, a portion of the paddle at theperiphery of the chip stack may be further connected (e.g., directlybonded together) to one or more other paddle to electrically tie a metalfeature on each chip to the same common reference potential (e.g., astacked-chip ground rail).

In some embodiments, a die-attach paste (DAP) or die-attach film (DAF)is disposed between one or more die of an assembly including an IC chipstack and stacked leads. The die-attach material may be employed toadhere IC chips together as a stacked die assembly is fabricated. In theexample shown in FIG. 2B, a first DAP/DAF 140A (e.g., an epoxy) isdisposed between IC chip 110 and base paddle 240. Base paddle 240 mayserve primarily as a substrate to which IC chip 110 is aligned andaffixed, for example by a pick-and-place operation, while die-attachpaddle 245A may make more direct thermal and/or electrical contact to ICchip 110. A layer of DAP/DAF material may be disposed between a chippaddle and each overlying IC chip. For example, DAP/DAF material 140D isdisposed between chip paddle 245C and IC chip 113. Assembly 201 isindicative of an assembly process in which chip 110 is first mounted tobase paddle 240 and held in place with DAP/DAF material 140 whiledie-attach lead 230A is bonded to chip 110. Bonding to chip 110 may beconcurrent with bonding to base lead 220. Chip 111 is then mounted todie-attach paddle 245A and held in place with DPA/DAF material 140 whileleadframe 230B is bonded to chip 111. Bonding to chip 111 may beconcurrent with bonding to die-attach lead 230A.

In some embodiments, stacked leads are bonded together forming avertical stack of leads with the bond point in substantial alignment ata periphery of the chip stack edge. As shown in FIG. 2B, lead stack 235Nincludes a bond point within region 250 where die-attach leads 230D,230C, 230B and 230A are all bonded together at the same lateral position(e.g., on x-axis) and die-attach lead 230A is further bonded to baselead 220. The footprint of assembly 201 is then a function of chiplength L_(c) and bond length Lb. Lateral overlap of the chips (L_(o) inFIG. 1B) may be eliminated because a chip is stacked over lead portions270 that are bonded to a metal feature (e.g., bond pad) of a chip. Sucha structure is indicative of lead portion 270 being bonded to a firstchip before a second chip is stacked on the first chip. As furthershown, deformation of each of the die-attach leads in stack 235N mayvary, for example with lower leads (e.g., 230A) having a larger bondfootprint than upper leads (e.g., 230D). In some embodiments where leadsare wedge-bonded, a wedge-bond employed for a lower leads (e.g., 230A)is of a larger diameter than that employed for an upper lead (e.g.,230D). Wedge bond diameter may be selected for each lead level of thestack to ensure a larger bond footprint of lead 230A is sufficientaccommodate a smaller bond footprint of lead 230B, which is in-turnsufficient to accommodate a next smaller bond footprint of lead 230C,etc. Depending on the bond footprint of the first die-attach lead andthe thickness of the die-attach leads, with each die-attach lead in astack the bonded surface area between two stacked leads may becomeprogressively more vertically-oriented (e.g., along the z-axis).Depending on the number of leads in a stack, the footprint of the firstdie-attach lead, and the thickness of the die-attach leads, one or morevoids may be present between leads within the bond footprint where awedge bond does not bottom out. For example, as shown in FIG. 2B, thereis a void between leads 230C and 230D within region 250. Electricalcontact is nevertheless provided through bonded surfaces of leads 230Cand 230D where they are deformed into vertical runs along the z-axis.

In some embodiments, there is no DAP/DAF material between an IC chipsand a lead and/or a chip paddle, in which case lead bonds are reliedupon to retain the chips during the assembly process. In the absence ofDAP/DAF material, an IC chip within the stack may be in direct contactwith both a first leadframe paddle on a first surface (e.g., top-side)and a second leadframe paddle on a second surface (e.g., bottom-side).The absence of DAP/DAF material may advantageously reduce z-height of astacked-chip assembly. The absence of DAP/DAF material may alsoadvantageously increase thermal conduction between chip paddles andadjacent chips under forced air-flow environments (e.g., a ventilatedpackage). In FIG. 3 for example, stacked-chip assembly 301 lacks DAP/DAFmaterial between IC chips 110-113 and die-attach leads 230A-230D. ICchips 111-113 are therefore only anchored by leads 230-233 and/orpaddles 245A-245D. In some such embodiments, chips are first mounted toa single leadframe and then the mounted chips are aligned when separateleadframes are stacked together. For example, in FIG. 3, IC chips110-113 may all be bonded to die-attach leadframes 230A-230D. A firstleadframe-mounted chip (e.g., 110) is then aligned with and bonded to abase leadframe including base paddle 240 and base lead 220. A secondleadframe-mounted chip (e.g., 111) including die-attach paddle 245B anddie-attach lead 230B is then aligned with, and bonded, to the die-attachleadframe including die-attach paddle 245A and die-attach lead 230A. Athird leadframe-mounted chip (e.g., 112) including die-attach paddle245C and die-attach lead 230C is then aligned with, and bonded to, thedie-attach leadframe including die-attach paddle 245B and die-attachlead 230B. A fourth leadframe-mounted chip (e.g., 113) includingdie-attach paddle 245D and die-attach lead 230D is then aligned with,and bonded to, the die-attach leadframe including die-attach paddle 245Cand die-attach lead 230C.

In some embodiments, a stacked-chip assembly includes a stack of chipsthat are “flipped” onto leads. In the context of a chip stack withleadframes, “flipping” is a reference to the orientation of IC chiprelative to a base leadframe. Once chips are mounted onto individualleadframes they may then be stacked with the chips in any orientation(chip up or leadframe up) and the peripheral leadframe portions bondedtogether. FIG. 4 illustrates a stacked lead assembly 401 in which eachof chips 110-113 make electrical connections to leads and/or chippaddles of an underlying leadframe. As shown, a base leadframe includesa base paddle 440 that has substantially the same footprint asdie-attach paddles 245A-245C. Base lead 220 makes electrical contactwith metal features (e.g., bond pads) on the face of IC chip 110 thatfaces the base leadframe. Base lead 220 therefore serves as more than asubstrate for assembly 401. Die-attach leads 230 are then disposed overIC chip 110, but do not make electrical contact to any metal features onIC chip 110. Instead, die-attach leads 230 make electrical contact tometal features on IC chip 111. Die-attach chip paddle 245A may makeelectrical contact to IC chip 110, for example to couple chip 110 to aground plane of the assembly 401. Die-attach chip paddle 245A may alsomake electrical contact to IC chip 111, for example to couple chip 111to a ground plane of the assembly 401. In the illustrated embodiment,chips of assembly 401 are separated by DAF/DAP material 140, which maybe employed to maintain positioning of the IC chips 110-113 until leadportions 250 are bonded together. Bonding of lead portions 250 may againbe incremental, performed with each successive leadframe layer.Alternatively, the bonding of all stacked leads may be a single eventperformed after the stack has been built up. Orientation of the IC chipsrelative to the leadframes may become obscured where the bonding processinduces lead deformation in the base and die-attach leads symmetricallywithin the z-axis. For example, FIG. 5 illustrates a stacked-chipassembly 501 where base lead 520 is deformed during lead bonding in amanner similar to die-attach lead 231. For embodiments where a baseleadframe has the same thickness and composition as a die-attachleadframe, the base leadframe may be indistinguishable in form andfunction from the die-attach leadframes, rendering assembly 501 nearlysymmetrical in the z-dimension.

In some embodiments, a mold compound is disposed between unboundedportions of a lead stack. The mold compound may be an epoxy with afiller, such as SiO₂. However, other mold compounds known to be suitablefor IC chip packaging may be employed. FIG. 6 illustrates an exemplaryassembly 601 in which mold compound 660 is disposed between leads 220,230A, 230B, 230C and 230D. Mold compound 660 may also fill recessesresulted from lead deformation within bonded lead portions 250. Moldcompound 660 may all fill in regions between stacked chips. For example,mold compound 660 may backfill recess between individual bonded leadportions 270, particularly if DAF/DAP material 140 is absent.

While all the embodiments described above advantageously lack bondwires, it is noted that leadframe stacking in accordance with someembodiments does not preclude the use of bond wires. A leadframe wirebonded to an IC chip may still be stacked upon another leadframe andbonded together at a periphery of the IC chip. Such embodiments maystill gain an advantage of reduced footprint relative to a waterfalledbond wire attachment. FIG. 7A illustrates a top-down plan view of astacked-chip assembly 701 including a stacked leadframe, in accordancewith one such alternate embodiment. FIG. 7B illustrates across-sectional view of stacked-chip assembly 701, in accordance withone such alternate embodiment. As shown, lead stacks 235A-235N areelectrically connected to IC chips by wires 770 which are bonded tostacked leads that are then bonded together within lead portions 250,substantially as described above in the context of FIG. 2A-FIG. 6. Suchan assembly is indicative of a leadframe stacking process that occursafter wire bonding a single IC chip to a single leadframe. Bonding ofthe leadframes may occur after all leadframes are stacked up orincrementally following the addition of each leadframe to the stack.

In accordance with some embodiments a stacked-chip assembly includingstack leads employs only one or two leadframe layouts. Reducing uniqueleadframe layouts advantageously reduces materials costs and increasesmanufacturing efficiency. FIG. 8A-8C illustrate an embodiment where alldie-attach leadframes have the same footprint, which is distinct fromthe base leadframe. FIG. 8A illustrates a plan view of base leadframe820, in accordance with some embodiments. Base leadframe 820 may bestamped out (e.g., after lead bonding) along dashed line 825 to providechip paddle 240 and base leads 220. FIG. 8B illustrates a plan view ofdie-attach leadframe 830, in accordance with some embodiments.Die-attach leadframe 830 may be stamped out (e.g., after lead bonding)along dashed line 825 to provide chip paddle 245 and base leads 230.With a plurality of die-attach leadframes 830 stacked over one baseleadframe 820, corresponding die-attach leads (e.g., 230A-230D in FIG.2A-FIG. 6) may therefore all overlay one another as well as base leads220. The leads may then be bonded together, for example with wedgebonding, and then stamped out of their surrounding foil frames (e.g.,along dashed line 825). Independent leads that are not to be stacked andbonded together may be provisioned, for example by wire-bonding only asubset of the leads in the leadframe, or by stamping of the leadframe toselectively bifurcate a subset of the leads in the leadframe.

FIG. 8C illustrate leadframe sheets 820 and 830, which may be employedin reel-to-reel packaging technology, in accordance with someembodiments. Base leadframe sheet 820 may include sprocket holes to berun through a reel-to-reel chip attachment process. Die-attach leadframesheet 830 may likewise include sprocket holes to be run through areel-to-reel chip attachment process. Multiple reels of leadframe sheets830 may be fed into a bonding/stamping apparatus where two or moreleadframe sheets 830 are overlaid. Stacked leadframe portions along aperiphery of the mounted chips are then pressed, deforming them as needto make contact to each other. The press may concurrently heat thestacked leadframe portions, bonding them together. The press may furthercut the bonded lead portions from the surrounding foil to separate thechip assembly from the respective reels. Any number of reels may besuperimposed and joined. Leadframe sheet lamination may be performed inan iterative, pairwise manner where the reel-to-reel process may take aninput of two reels (e.g., two die-attach sheets 831 or one die-attachsheet 831 and one base sheet 820) and output a single bonded sheet. Thatbonded sheet may then be fed into another 2:1 reel-to-reel process wherethe bonded sheet is then laminated to another sheet. At any point, whenenough leadframe sheets have been bonded, the assembly may be punchedfree from the laminate leadframe sheet, for example along the dashedline 825. In alternative embodiments, leadframe sheet lamination isperformed with three or more input reels where two or more die-attachsheets 831 and one base sheet 820 are input and all sheets areconcurrently bonded together and the resulting stacked-chip assemblypunched out of the leadframe laminate. A pre-press may be furtheremployed to deform and/or cut various leads and lead portions before orafter a chip is mounted to the leadframe sheet.

FIG. 9A, 9B illustrate flow diagrams of methods 901, 902 for assemblinga stacked-chip assembly including stacked leads, in accordance with someexemplary embodiments. Methods 901, 902 may, for example, be employed toassemble one or more of the assemblies described above.

Referring first to FIG. 9A, method 901 begins with receiving IC chips,such as, but not limited, to memory chips (e.g., flash memory chips,such as NAND). A base leadframe sheet is also received as an input tomethod 901. At operation 905, a first IC chip is attached to the baseleadframe sheet using any technique known to be suitable for the metalfeatures of the IC chip and the base leadframe. For example, the IC chip110 is aligned and affixed to a chip paddle portion of the baseleadframe sheet, as further shown in FIG. 9B, which illustratescross-sectional views of a stacked-chip assembly as selected operationsin the assembly method 901 is performed, in accordance with someembodiments. A pre-press may have been employed upstream of operation905 to deform and/or cut various leads and lead portions before the ICchip is mounted to the leadframe sheet.

Continuing with FIG. 9A, operation 915 receives a die-attach leadframesheet as a further input. A pre-press may have been employed upstream ofoperation 915 to deform and/or cut various leads and lead portions. Atoperation 915, the die-attach leadframe is bonded to the first IC chip.For example, a paddle portion of the die-attach leadframe may be bondedto a center portion of the first IC chip and first ends of lead portionsof the die-attach leadframe may be bonded to separate metal features ofthe first IC chip. The paddle and lead portions may all be bondedconcurrently in a thermal-compression bonder, for example. Method 925continues where a second IC chip is attached to the die-attachleadframe, for example with a DAF/DAP material. At this point, asfurther shown in FIG. 9B, the stacked-chip assembly includes two ICchips and two leadframes bonded together.

Returning to FIG. 9A, a second die attach leadframe is bonded to thesecond IC chip at operation 935. For example, a paddle portion of thedie-attach leadframe may be bonded to a center portion of the second ICchip and first ends of lead portions of the die-attach leadframe may bebonded to separate metal features of the second IC chip. The paddle andlead portions may all be bonded concurrently in a thermal-compressionbonder, for example. Method 901 may iterated through operations 915, 925and 935, as denoted by the dashed arrow in FIG. 9A, to build up astacked-chip assembly that includes any desired number of IC chips andleadframes (e.g., to arrive at assembly 201, as further illustrated inFIG. 9B).

Method 901 (FIG. 9A) then continues through an optional moldingoperation where a mold compound is flowed between unbounded portions ofthe leadframe stack. Mold compound may be applied while the stackedleadframes are still in sheet form, or after the assemblies areseparated from the leadframe sheets. Separated assemblies may be mountedto a front or back-side tape at operation 940 to facilitatemolding/encapsulation of the stack chip assembly at operation 950. Wherethe assemblies are molded while still mounted to leadframe sheets,taping operation 940 may be skipped. At operation 960, the assemblies,molded or not, are singulated, for example using any technique known.The output of method 901 is then a stacked-chip assembly including stackleads, for example as described elsewhere herein.

Referring to FIG. 9C, method 902 exemplifies some alternate embodimentswhere IC chips are first mounted to individual leadframes and then thechip-mounted leadframes stacked and bonded. Die attach operation 905receives first IC chips, such as but not limited to, memory chips (e.g.,flash memory chips, such as NAND), and receives a base leadframe sheet.A pre-press may have been employed upstream of operation 905 to deformand/or cut various leads and lead portions. In some embodiments, the ICchips are epoxied or otherwise adhered to the base leadframe sheet. Insome other embodiments, the IC chips are bonded to the base leadframesheet with the each of the bonds making an electrical connections to oneof the IC chips. Die attach operation 910 receives second IC chips, suchas, but not limited to memory chips (e.g., flash memory chips, such asNAND), and receives a die-attach leadframe sheet. The second IC chipsare bonded to the die-attach leadframe sheet with each of the bondsmaking an electrical connection to one of the IC chips. A pre-press mayhave been employed upstream of operation 910 to deform and/or cutvarious leads and lead portions. For embodiments where the baseleadframe and die-attach leadframe are the same, operations 905 and 910may be merged into a single die-attach operation that is repeated togenerate a plurality of chip-mounted leadframe sheets. At operation 920,leadframe sheets are aligned one over the other and bonded, for examplewith a thermal compression wedge bonder, to join spatially co-locatedleads forming a lead stack. At operation 930, a second die-attachleadframe having another mounted IC chip is aligned over the stack-upand bonded to the first die-attach leadframe to increase the stackedchip count. Alternatively, operations 920 and 930 may be performedconcurrently with more than two unbounded leadframe sheets being alignedrelative to each other and bonded together with one thermo-compressionbonding process. Operation 930 may be repeated as desired to increasethe IC chip count. Method 901 then continues through an optional moldingoperation where a mold compound is flowed between unbounded portions ofthe leadframe stack. Mold compound may be applied while the stackedleadframes are still in sheet form, or after the assemblies areseparated from the leadframe sheets. Separated assemblies may be mountedto a front or back-side tape at operation 940 to facilitatemolding/encapsulation of the stack chip assembly at operation 950. Wherethe assemblies are molded while still mounted to leadframe sheets,taping operation 940 may be skipped. At operation 960, the assemblies,molded or not, are singulated, for example using any technique known.The output of method 901 is then a stack chip assembly including stackleads, for example as described elsewhere herein.

FIG. 10 is a functional block diagram of an electronic computing device,in accordance with an embodiment of the present invention. Device 1000further includes a motherboard 1002 hosting a number of components, suchas, but not limited to, a processor 1004 (e.g., an applicationsprocessor). Processor 1004 may be physically and/or electrically coupledto motherboard 1002. In some examples, processor 1004 includes anintegrated circuit die packaged within the processor 1004. In general,the term “processor” or “microprocessor” may refer to any device orportion of a device that processes electronic data from registers and/ormemory to transform that electronic data into other electronic data thatmay be further stored in registers and/or memory.

In various examples, one or more communication chips 1006 may also bephysically and/or electrically coupled to the motherboard 1002. Infurther implementations, communication chips 1006 may be part ofprocessor 1004. Depending on its applications, computing device 1000 mayinclude other components that may or may not be physically andelectrically coupled to motherboard 1002. These other componentsinclude, but are not limited to, volatile memory (e.g., DRAM),non-volatile memory (e.g., ROM), flash memory (e.g., NAND or NOR), agraphics processor, a digital signal processor, a crypto processor, achipset, an antenna, touchscreen display, touchscreen controller,battery, audio codec, video codec, power amplifier, global positioningsystem (GPS) device, compass, accelerometer, gyroscope, speaker, camera,and mass storage device (such as hard disk drive, solid-state drive(SSD), compact disk (CD), digital versatile disk (DVD), and so forth),or the like. In some exemplary embodiments, at least the flash memorycomprises a stacked-chip assembly including stacked leads, for exampleas described elsewhere herein.

Communication chips 1006 may enable wireless communications for thetransfer of data to and from the computing device 1000. The term“wireless” and its derivatives may be used to describe circuits,devices, systems, methods, techniques, communications channels, etc.,that may communicate data through the use of modulated electromagneticradiation through a non-solid medium. The term does not imply that theassociated devices do not contain any wires, although in someembodiments they might not. Communication chips 1006 may implement anyof a number of wireless standards or protocols, including but notlimited to those described elsewhere herein. As discussed, computingdevice 1000 may include a plurality of communication chips 1006. Forexample, a first communication chip may be dedicated to shorter-rangewireless communications, such as Wi-Fi and Bluetooth, and a secondcommunication chip may be dedicated to longer-range wirelesscommunications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, andothers.

FIG. 11 illustrates a mobile computing platform and a data servermachine employing a stacked memory chip assembly including stack leads,for example as described elsewhere herein. Computing device 1000 may befound inside platform 1105 or server machine 1106, for example. Theserver machine 1106 may be any commercial server, for example includingany number of high-performance computing platforms disposed within arack and networked together for electronic data processing, which in theexemplary embodiment includes a packaged monolithic SoC 1150. The mobilecomputing platform 1105 may be any portable device configured for eachof electronic data display, electronic data processing, wirelesselectronic data transmission, or the like. For example, the mobilecomputing platform 1105 may be any of a tablet, a smart phone, laptopcomputer, etc., and may include a display screen (e.g., a capacitive,inductive, resistive, or optical touchscreen), a chip-level orpackage-level integrated system 1110, and a battery 1115.

Whether disposed within the integrated system 1110 illustrated in theexpanded view 1120, or as a stand-alone chip within the server machine1106, stacked memory chip assembly 1150 includes a plurality of memorychips and a plurality of stacked leads, for example as describedelsewhere herein. Memory chip stack 1150 may be further coupled to aboard, a substrate, or an interposer 1160 along with, one or more of apower management integrated circuit (PMIC) 1130, RF (wireless)integrated circuit (RFIC) 1125 including a wideband RF (wireless)transmitter and/or receiver (TX/RX) (e.g., including a digital basebandand an analog front end module further comprises a power amplifier on atransmit path and a low noise amplifier on a receive path), and acontroller 1135.

Functionally, PMIC 1130 may perform battery power regulation, DC-to-DCconversion, etc., and so has an input coupled to battery 1115 and withan output providing a current supply to other functional modules. Asfurther illustrated, in the exemplary embodiment, RFIC 1125 has anoutput coupled to an antenna (not shown) to implement any of a number ofwireless standards or protocols, including but not limited to Wi-Fi(IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long termevolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA,TDMA, DECT, Bluetooth, derivatives thereof, as well as any otherwireless protocols that are designated as 3G, 4G, 4G, and beyond.

While certain features set forth herein have been described withreference to various implementations, this description is not intendedto be construed in a limiting sense. Hence, various modifications of theimplementations described herein, as well as other implementations,which are apparent to persons skilled in the art to which the presentdisclosure pertains are deemed to lie within the spirit and scope of thepresent disclosure.

In one or more first embodiments, an integrated circuit (IC) chipassembly comprises an IC chip stack including at least a first andsecond IC chip, and a lead stack including at least a first and secondlead, the first lead electrically coupled to at least the first IC chipand bonded to the second lead at a periphery of the chip stack, thesecond lead electrically coupled to at least the second IC chip.

In one or more second embodiments, for the IC chip assembly in any ofthe first embodiments, the first lead includes a first portion bonded toa first metal feature of the first chip, the second lead includes afirst portion bonded to the first metal feature of the second chip, andthe first and leads include second portions that are bonded together.

In one or more third embodiments, for the IC chip assembly in any of thefirst or second embodiments, the lead stack includes a base lead and adie-attach lead disposed over the base lead, the first chip is disposedbetween the base lead and the die-attach lead, the second chip isdisposed over the die-attach lead, and a first die-attach lead is bondedto a first base lead at the periphery of the chip stack.

In one or more fourth embodiments, for the IC chip assembly in any ofthe third embodiments, the first die-attach lead is bonded to a metalfeature of the first or second chip.

In one or more fifth embodiments, for the IC chip assembly in any of thethird embodiments, the die-attach lead further comprises a firstdie-attach lead and a second die-attach lead, the first chip is disposedbetween the base lead and the first die-attach lead, the second chip isdisposed between the first and second die-attach leads, a portion of thefirst die-attach lead is bonded to the base lead, and a portion thesecond die-attach lead is bonded to the bonded portion of the firstdie-attach lead.

In one or more sixth embodiments, for the IC chip assembly in any of thefifth embodiments, a portion of the first die-attach lead is bonded to ametal feature of the first chip, and a portion of the second die-attachlead is bonded to a metal feature of the second chip.

In one or more seventh embodiments, the IC chip assembly in any of thefirst, second, third, fourth, fifth, or sixth embodiments furtherincludes a metal paddle disposed between the first and second IC chips,the paddle electrically isolated from at least one of the leads.

In one or more eighth embodiments, the IC chip assembly in any of thefirst, second, third, fourth, fifth, sixth seventh embodiments furtherincludes a metal paddle disposed between first and second IC chips, thepaddle electrically coupling each of the chips to a common referencevoltage rail.

In one or more ninth embodiments, the IC chip assembly in any of thefirst, second, third, fourth, fifth, sixth seventh, or eighthembodiments further comprises a die-attach paste or film disposedbetween at least one of the leads and the first or second IC chip.

In one or more tenth embodiments, the IC chip assembly in any of thefirst, second, third, fourth, fifth, sixth seventh, eighth, or ninthembodiments further comprises a mold compound disposed between unbondedportions of the first and second leads.

In one or more eleventh embodiments, an integrated circuit (IC) platformcomprises a substrate including a plurality of signal pads, and the ICchip assembly in any of the first, second, third, fourth, fifth, sixth,seventh, eighth, ninth, or tenth embodiments, wherein the first lead iselectrically coupled to one of the signal pads.

In one or more twelfth embodiments, for the IC platform in the eleventhembodiments, the substrate further includes a ground pad, and the ICchip assembly further includes a metal paddle disposed between the firstIC chip and the substrate, the metal paddle electrically isolated fromthe first lead and electrically coupled to the ground pad.

In one or more thirteenth embodiments, for the IC platform in thetwelfth embodiments, the IC chips comprise a plurality of NAND flashmemory chips.

In one or more fourteenth embodiments, a method of assembling anintegrated circuit (IC) chip stack comprises stacking a first and secondleadframe, and bonding first leads of the first leadframe tocorresponding second leads of the second leadframe that are stacked overthe first leads, the bonded first leads further coupled to a first ICchip and the bonded second leads further coupled to a second IC chipstacked over the first.

In one or more fifteenth embodiments, the method in any of thefourteenth embodiments further comprises attaching the first leadframeto the first IC chip, attaching the second leadframe to the second ICchip, and singulating the chip stack from the stacked leadframes at alocation beyond the lead-to-lead bonds to maintain electrical continuitybetween the stacked leads.

In one or more sixteenth embodiments, the method in any of thefourteenth or fifteenth embodiments further comprises stacking thesecond chip over the first chip prior to attaching the second leadframeto the second IC chip.

In one or more seventeenth embodiments, the method in any of thefourteenth or fifteenth embodiments further comprises attaching thesecond leadframe to the second IC chip prior to stacking the second chipover the first chip.

In one or more eighteenth embodiments, in the method of the fourteenthor fifteenth embodiments, attaching the first leadframe to the firstchip further comprises bonding the first leads to metal features on afront-side surface of the first chip, attaching the second leadframefurther comprises bonding the second leads to metal features on afront-side surface of the second chip, and bonding the first leads tothe second leads further comprises wedge-bonding the second leads to thefirst leads at a location beyond an edge of the first and second chips.

In one or more nineteenth embodiments, the method of the eighteenthembodiments further comprises adhering a back-side surface of the firstIC chip a paddle of a base leadframe, and bonding the first leads tocorresponding leads of the base leadframe prior to bonding the secondleads to the first leads.

In one or more twentieth embodiments, the method of the eighteenthembodiments further comprises adhering a back-side surface the secondchip to the first leadframe before bonding the second leadframe to thesecond chip.

It will be recognized that the invention is not limited to theembodiments so described, but can be practiced with modification andalteration without departing from the scope of the appended claims. Forexample the above embodiments may include specific combinations offeatures as further provided below.

What is claimed is:
 1. An integrated circuit (IC) chip assembly,comprising: a first IC chip; a second IC chip in a stack with the firstIC chip; a paddle between the first and second IC chips, wherein thepaddle comprises metal and includes a paddle end that is coupled to atleast one of a metal feature at a periphery of the stack, or a heatsink.
 2. The IC chip assembly of claim 1, wherein the paddle end iscoupled to a metal feature at a periphery of the stack, and wherein thepaddle makes electrical contact to a metal feature on one or both of thefirst and second IC chips.
 3. The IC chip assembly of claim 2, whereinthe paddle electrically couples each of the IC chips to a commonreference voltage rail.
 4. The IC chip assembly of claim 2, furthercomprising a substrate including a ground pad, and where the paddle endis bonded to the ground pad.
 5. The IC chip assembly of claim 1,wherein: the paddle is a first paddle and the assembly further comprisesa second paddle; the second paddle comprises a metal, a paddle end ofthe first paddle is bonded to a paddle end of the second paddle at theperiphery of the chip stack.
 6. The IC chip assembly of claim 1, furthercomprising a base paddle coupled to a side of the first chip oppositethe paddle between the first and second chips, and wherein an area ofthe base paddle is larger than an area of the paddle between the firstand second chips.
 7. The IC chip assembly of claim 1, further comprisinga first lead and a second lead, the first lead electrically coupled toat least the first IC chip; and a second lead electrically coupled to atleast the second IC chip, and bonded to the second lead at the peripheryof the chip stack.
 8. The IC chip of claim 7, wherein the paddle iselectrically isolated from at least one of the first or second leads. 9.The IC chip of claim 8, further comprising a substrate including aplurality of signal pads; and wherein the first lead is electricallycoupled to one of the signal pads.
 10. The IC platform of claim 12,wherein the IC chips comprise a plurality of NAND flash memory chips.11. The IC chip assembly of claim 1, further comprising a die-attachpaste or film disposed between at least one of the leads and the firstor second IC chip.
 12. An integrated circuit (IC) platform, comprising:a substrate including a plurality of signal pads; three of more memorychips in a stack; a paddle between each of the memory chips, wherein:the paddle comprises a metal and includes one or more paddle ends; apaddle end of each paddle is coupled to at least one of a metal featureof the substrate at a periphery of the stack, or a heat sink; and aplurality of signal leads electrically coupled to each of the chips andto the signal pads.
 13. The IC platform of claim 12, wherein the metalfeature comprises a ground pad and wherein the paddles are electricallyisolated from the signal leads.
 14. The IC platform of claim 12, whereinthe signal leads comprise a plurality of a die-attach leads, a first endof spatially co-located ones of the die-attach leads bonded together atthe periphery of the stack, and a second end of the die-attach leadsbonded to a metal feature on separate ones of the chips.
 15. The ICplatform of claim 12, wherein the memory chips are NAND memory chipswith substantially the same footprint and the same pin-out padlocations.
 16. A method of assembling an integrated circuit (IC) chipstack, the method comprising: attaching a first leadframe to a first ICchip, the first leadframe including a first paddle under the first ICchip; attaching a second leadframe to a second IC chip, the secondleadframe including a second paddle under the second IC chip; stackingthe first and second leadframes with the second paddle between the firstand second first and second IC chips; bonding ends of the first andsecond paddle together; and singulating the chip stack from the stackedleadframes at a location beyond the bonded paddle ends to maintainelectrical continuity between the first and second paddles.
 17. Themethod of claim 16, further comprising bonding first leads of the firstleadframe to corresponding second leads of the second leadframe that arestacked over the first leads, the bonded first leads further coupled tothe first IC chip, and the bonded second leads further coupled to thesecond IC chip.
 18. The method of claim 17, wherein: attaching the firstleadframe to the first chip further comprises bonding the first leads tometal features on a front-side surface of the first IC chip; attachingthe second leadframe further comprises bonding the second leads to metalfeatures on a front-side surface of the second IC chip; and bonding thefirst leads to the second leads further comprises wedge-bonding thesecond leads to the first leads at a location beyond an edge of thefirst and second IC chips.
 19. The method of claim 17, furthercomprising: adhering a back-side surface of the first IC chip to thepaddle of the first leadframe; and bonding the first leads tocorresponding leads of a base leadframe prior to bonding the secondleads to the first leads.
 20. The method of claim 19, further comprisingadhering a back-side surface a third IC chip to a paddle of the baseleadframe before bonding the first leadframe to the base leadframe.